Design and Implementation of Decimation Filter for 15-bit Sigma-Delta ADC Based on FBGA
نویسندگان
چکیده
A 15 bit Sigma-Delta ADC for a signal band of 40K Hz is designed in MATLAB Simulink and then implemented using Xilinx system generator tool. The second order SigmaDelta modulator is designed to work at a signal band of 40 KHz at an Oversampling ratio (OSR) of 128 with a sampling frequency of 10.24 MHz. The proposed decimation filter design is consists of a third order Cascaded Integrator Comb filter (CIC) followed by two finite impulse response filters. This architecture reduces the need for multiplication which is need very large area. This architecture implements a decimation ratio of 128 and allows a maximum resolution of 15 bits in the output of the filter. The decimation filter was designed and tested in Xilinx system generator tool which reduces the design cycle by directly generating efficient VHDL code. The results obtained show that the overall Sigma-Delta ADC is able to achieve an ENOB (Effective Number of Bit) of 14.73bits and SNR of 90.4dB.
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